Efficient Scalable Hardware Architecture for Montgomery Inverse Computation in GF(P)

(2003) Efficient Scalable Hardware Architecture for Montgomery Inverse Computation in GF(P). In: IEEE Workshop on Signal Processing Systems (SIPS’03), August 27-29, 2003, Seoul, Korea.

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Abstract

The Montgomery inversion is a fundamental computation in several cryptographic applications. In this work, we propose a scalable hardware architecture to compute the Montgomery modular inverse in GF(p). We suggest a new correction phase for a previously proposed almost Montgomery inverse algorithm to calculate the inversion in hardware. The intended architecture is scalable, which means that a fixed-area module can handle operands of any size. The word-size, which the module operates, can be selected based on the area and performance requirements. The upper limit on the operand precision is dictated only by the available memory to store the operands and internal results. The scalable module is in principle capable of performing infinite-precision Montgomery inverse computation of an integer, modulo a prime number. This scalable hardware is compared with a previously proposed fixed (fully parallel) design showing very attractive results.

Item Type: Conference or Workshop Item (Paper)
Subjects: Math
Computer
Systems
Electrical
Divisions: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: ADNAN ABDU GUTUB (gutub
Date Deposited: 17 May 2008 08:31
Last Modified: 01 Nov 2019 16:26
URI: http://eprints.kfupm.edu.sa/id/eprint/1300