(2003) Fast Elliptic Curve Cryptographic Processor Architecture Based On Three Parallel GF(2k) Bit Level Pipelined Digit Serial Multipliers. In: IEEE 10th International Conference on Electronics, Circuits and Systems (ICECS 2003), December 14-17, 2003, University of Sharjah, United Arab Emirates.

	HTML (Abstract) C_c.htm Download (6kB)
Preview	PDF (Paper) C_C.pdf Download (74kB) | Preview

Abstract

Unusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2k) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2k) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography.

Item Type:	Conference or Workshop Item (Paper)
Subjects:	Math Computer Systems Electrical
Department:	College of Computing and Mathematics > Computer Engineering
Depositing User:	ADNAN ABDU GUTUB (gutub
Date Deposited:	17 May 2008 05:31
Last Modified:	01 Nov 2019 13:26
URI:	http://eprints.kfupm.edu.sa/id/eprint/1298