Scalable VLSI Design for Fast GF(p) Montgomery Inverse Computation

(2006) Scalable VLSI Design for Fast GF(p) Montgomery Inverse Computation. In: IEEE International Conference on Computer & Communication Engineering (ICCCE '06), 9-11 May 2006, Faculty of Engineering, International Islamic University Malaysia, Kuala Lumpur, Malaysia.

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Abstract

This paper accelerates a scalable GF(p) Montgomery inversion hardware. The hardware is made of two parts a memory and a computing unit. We modified the original memory unit to include parallel shifting of all bits which was a task handled by the computing unit. The new hardware modeling, simulating, and synthesizing is performed through VHDL for several 160-bits designs showing interesting speedup to the inverse computation.

Item Type: Conference or Workshop Item (Paper)
Subjects: Math
Computer
Systems
Electrical
Divisions: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: ADNAN ABDU GUTUB (gutub
Date Deposited: 17 May 2008 08:33
Last Modified: 01 Nov 2019 16:26
URI: http://eprints.kfupm.edu.sa/id/eprint/1290