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    Research note. A CMOS cell for parallelly loadable counters

    (1987) Research note. A CMOS cell for parallelly loadable counters. International Journal of Electronics,, 63 (6). pp. 867-871.

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    Abstract

    A CMOS flip-flop cell which can be used in counters is designed. SPICE model, the transient response and the CMOS layout are presented. When used in counters, the flip-flop can be loaded to initialize the count.

    Item Type: Article
    Subjects: Electrical
    Department: College of Engineering and Physics > Electrical Engineering
    Depositing User: ANKAR (g200603940) (g200603940)
    Date Deposited: 12 May 2008 08:00
    Last Modified: 01 Nov 2019 13:26
    URI: http://eprints.kfupm.edu.sa/id/eprint/1268