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    Design, Selection and Implementation of Flash Erase EEPROM Memory Cell Structures

    (1992) Design, Selection and Implementation of Flash Erase EEPROM Memory Cell Structures. IEE Proceedings G on Circuits, Devices and Systems, 139 (3). pp. 370-376.

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    Abstract

    The author reports an investigation into the design and process constraints of flash EEPROM memory cells. He describes several possible structures which were developed by the MOS memory R&D group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested on a specially designed test chip. In addition to the typical structures of poly 1 floating gate and poly 2 control gate, new novel structures of poly 2 floating gate and poly 1 control gate were implemented. A total of five major structures are described. The author discusses the principle of operation, advantages and disadvantages of each of these structures. Also included are characteristic results and a discussion of the performance of these candidate cells

    Item Type: Article
    Subjects: Computer
    Department: College of Computing and Mathematics > Computer Engineering
    Depositing User: Obaid-Ur-Rehman Khattak
    Date Deposited: 28 Apr 2008 12:33
    Last Modified: 01 Nov 2019 13:26
    URI: http://eprints.kfupm.edu.sa/id/eprint/1234

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