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    Back-end design of a formal high level synthesis system

    (1993) Back-end design of a formal high level synthesis system. Masters thesis, King Fahd University of Petroleum and Minerals.

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    Arabic Abstract

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    English Abstract

    A complete design and implementation of a cell library has been accomplished in this work. This cell library supports a formal high level synthesis framework. The library contains the logic level models of all the primitive functions of a Realization Specification Language (RSL). Moduler design methodology is employed to support the expandibility of basic cells. Examples of a formal adder, multiplier, inner-product and matrix-matrix multiplier are presented.

    Item Type: Thesis (Masters)
    Subjects: Computer
    Department: College of Computing and Mathematics > Computer Engineering
    Committee Advisor: Sait, Sadiq M.
    Committee Members: Elleithy, Khaled M. and Youssef, Habib
    Depositing User: Mr. Admin Admin
    Date Deposited: 22 Jun 2008 13:57
    Last Modified: 01 Nov 2019 13:57
    URI: http://eprints.kfupm.edu.sa/id/eprint/10156