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Items where Author is "El-Maleh, Aiman H."

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Article

Alghonaim, Esa and Andalusi, Adnan and El-Maleh, Aiman H. (2007) IMPROVING BER PERFORMANCE OF LDPC CODES BASED ON INTERMEDIATE DECODING RESULTS. IEEE International Conference on Signal Processing and Communications. pp. 1547-1550.

Alghonaim, Esa and El-Maleh, Aiman H. and Andalusi, Adnan (2007) PARALLEL COMPUTING PLATFORM FOR EVALUATING LDPC CODES PERFORMANCE. IEEE International Conference on Signal Processing and Communications. pp. 157-160.

El-Maleh, Aiman H. and Ali, Mustafa I. and Al-Yamani, Ahmad A. (2007) A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition. 16th IEEE Asian Test Symposium. pp. 91-94.

El-Maleh, Aiman H. and Khursheed, S. Saqib (2007) Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering. IET Computers & Digital Techniques, 1 (4). pp. 364-368.

El-Maleh, Aiman H. and Arkasosy, Basil and Andalusi, Adnan (2006) Interconnect-Efficient LDPC Code Design. 18th IEEE Int. Conf. on Microlelectronics. pp. 127-130.

El-Maleh, Aiman H. and Khursheed, S. Saqib (2006) Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering. IEEE Int. Design and Test Workshop.

El-Maleh, Aiman H. and Khursheed, S. Saqib and Sait, Sadiq M. (2006) Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 25 (11): 2556-2564 NOV 2006.

El-Maleh, Aiman H. (2006) An Efficient Test Vector Compression Technique Based on Block Merging. IEEE Int. Symp. on Circuits and Systems. pp. 1447-1450.

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, RH (2006) Evolutionary algorithms for VLSI multi-objective netlist partitioning. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 19 (3): 257-268 APR 2006. ISSN 0952-1976

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, RH (2006) Evolutionary Algorithms for VLSIMultiobjective Netlist Partitioning. ENGINEERING INTELLIGENT SYSTEMS FOR ELECTRICAL ENGINEERING AND COMMUNICATIONS 13 (1): 15-21 MAR 2005.

El-Maleh, Aiman H. and Sait, Sadiq M. and Shazli, Syed Z. (2005) Evolutionary algorithms for state justification in sequential automatic test pattern generation.

El-Maleh, Aiman H. and Osais, Yahya E. (2004) A Class-based Clustering Static Compaction Technique for Combinational Circuits. 16th International Conference on Microelectronics. pp. 522-525.

El-Maleh, Aiman H. and Osais, Yahya E. (2004) On Test Vector Reordering for Combinational Circuits. 16th International Conference on Microelectronics. 772 -775.

El-Maleh, Aiman H. and Al-Utaibi, Khaled (2004) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits, 23 (6). pp. 933-940.

El-Maleh, Aiman H. (2003) A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip. 10th IEEE International Conference on Electronics, Circuits and Systems,. pp. 599-602.

Osais, Yahya E. and El-Maleh, Aiman H. (2003) A STATIC TEST COMPACTION TECHNIQUE FOR COMBINATIONAL CIRCUITS BASED ON INDEPENDENT FAULT CLUSTERING. 10th IEEE International Conference on Electronics, Circuits and Systems. pp. 1316-1319.

El-Maleh, Aiman H. and Osais, Yahya E. (2003) Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits. ACM Transactions on Design Automation of Electronic Systems, 8 (4). pp. 430-459.

El-Maleh, Aiman H. and Al-Utaibi, Khaled (2003) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE International Symposium on Circuits and Systems. V-545 -V-548.

El-Maleh, Aiman H. and Al-Utaibi, Khaled (2003) ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS. IEEE International Symposium on Circuits and Systems. V-545 -V-548.

El-Maleh, Aiman H. and Al-Suwaiyan, Ali (2002) An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing. 9th IEEE International Conference on Electronics, Circuits and Systems. pp. 461-465.

El-Maleh, Aiman H. and Al-Abaji, Raslan H. (2002) Extended Frequency-Directed Run-Length Code with Improved Application to System-on-a-Chip Test Data Compression. 9th IEEE International Conference on Electronics, Circuits and Systems. pp. 449-452.

El-Maleh, Aiman H. and Al-Suwaiyan, Ali (2002) An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 20’th IEEE VLSI Test Symposium. pp. 53-59.

Al Zahir, Saif and El-Maleh, Aiman H. and Khan, Esam (2001) An Efficient Test Vector Compression Technique Based on Geometric Shapes. 8th IEEE International Conference on Electronics, Circuits and Systems. pp. 1561-1564.

El-Maleh, Aiman H. and Sait, Sadiq M. and Shazli, Syed Z. (2001) An Evolutionary Meta-Heuristic for State Justification in Sequential Automatic Test Pattern Generation. International Joint INNS-IEEE Conference on Neural Networks (IJCNN). pp. 767-772.

El-Maleh, Aiman H. and Al Zahir, Saif and Khan, Esam (2001) A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. 19’th IEEE VLSI Test Symposium (VTS). pp. 54-59.

El-Maleh, Aiman H. and Sait, Sadiq M. and Shazli, Syed Z. (2001) An Iterative Heuristic for State Justi�cation in Sequential Automatic Test Pattern Generation. Genetic and Evolutionary Computation Conference (GECCO).

El-Maleh, Aiman H. and Osais, Yahya E. (2001) A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures. Int. Symp. on Circuits and Systems. pp. 550-553.

El-Maleh, Aiman H. and Kassab, Mark and Rajski, Janusz (1998) A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. 32nd Design Automation Congference. pp. 625-631.

Cheng, Wu-Tung and Thompson, Rob and El-Maleh, Aiman H. and Ross, Don and Rajski, Janusz (1997) The Pitfalls of Necessary Assignments. Fourth International Test Synthesis Workshop.

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, Raslan H. EVOLUTIONARY HEURISTICS FOR MULTIOBJECTIVE VLSI NETLIST BI-PARTITIONING. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

El-Maleh, Aiman H. and Al-Abaji, Raslan H. ON IMPROVING THE EFFECTIVENESS OF SYSTEM-ON-ACHIP TEST DATA COMPRESSION BASED ON EXTENDED FREQUENCY DIRECTED RUN-LENGTH CODES. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

Sait, Sadiq M. and El-Maleh, Aiman H. STATE MACHINE SYNTHESIS WITH WEINBERGER ARRAYS. INTERNATIONAL JOURNAL OF ELECTRONICS 71 (1): 1-12 JUL 1991.

Conference or Workshop Item

El-Maleh, Aiman H. and Sait, Sadiq M. and Khan, Faisal N. (2006) Finite State Machine State Assignment for Area and Power Minimization. In: Proceedings of 2006 International Symposium in Circuits and Systems, (ISCAS 2006), Island of Kos, Greece.

El-Maleh, Aiman H. and Khursheed, S. Saqib and Sait, Sadiq M. (2005) Efficient Static Compaction Techniques for Sequential Circuits based on Reverse Order Restoration Based and Test Relaxation. In: Proceedings of the 14th Asian Test Symposium (ATS ’05), Kolkata, India.

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, Raslan H. (2005) Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning. In: Unknown.

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, RH (2003) ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING. In: IEEE International Symposium on Circuits and Systems, Sharjah, UAE.

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, RH (2003) Simulated Evolution Algorithm For Multiobjective VLSI Netlist Bi-Partitioning. In: IEEE International Symposium on Circuits and Systems', Bangkok, Thailand.

Sait, Sadiq M. and El-Maleh, Aiman H. and Al-Abaji, RH (2003) GENERAL ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

Sait, Sadiq M. and Youssef, H. and El-Maleh, Aiman H. and Minhas, Mahmood R. (2001) Iterative Heuristics for Multiobjective VLSI Cell Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

Sait, Sadiq M. and Youssef, H. and El-Maleh, Aiman H. (2001) Iterative Heuristics for Timing & low power VLSI standard cell placement. In: Unknown. (Unpublished)

El-Maleh, Aiman H. and Sait, Sadiq M. (1991) A State Machine Synthesizer with Weinberger Arrays. In: The IEEE Pacific RIM Conference, Victoria, Canada.

El-Maleh, Aiman H. and Sait, Sadiq M. and Shazli, Syed Z. An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation. In: An Iterative Heuristic for State Justification in, Dhahran, Saudi Arabia.

Sait, Sadiq M. and Youssef, H. and El-Maleh, Aiman H. Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. In: KFUPM Project Number COE/ITERATE/221, KFUPM.

This list was generated on Sun Apr 20 08:43:49 2014 AST.