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Items where Author is "El-Maleh, A."

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Number of items: 9.

Article

El-Maleh, A. and Sait, Sadiq M. and Nawaz Khan, F. (2006) Finite state machine state assignment for area and power minimization. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 1.

El-Maleh, A. and Al-Utaibi, K. (2003) On efficient extraction of partially specified test sets for synchronous sequential circuits. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

El-Maleh, A. and Al-Utaibi, K. (2003) An efficient test relaxation technique for synchronous sequential circuits. VLSI Test Symposium, 2003. Proceedings. 21st, 1.

El-Maleh, A. and Al-Suwaiyan, A. (2002) An efficient test relaxation technique for combinational & full-scan sequential circuits. VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, 1.

El-Maleh, A. and Al-Suwaiyan, A. (2002) An efficient test relaxation technique for combinational circuits based on critical path tracing. Electronics, Circuits and Systems, 2002. 9th International conference, 2.

Sait, Sadiq M. and Youssef, H. and Khan, J.A. and El-Maleh, A. (2001) Fuzzified iterative algorithms for performance driven low powerVLSI placement. Computer Design, 2001. ICCD 2001. Proceedings. 2001 International conference, 1.

Sait, Sadiq M. and Youssef, H. and Khan, J.A. and El-Maleh, A. (2001) Fuzzy simulated evolution for power and performance optimization ofVLSI placement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

El-Maleh, A. and al Zahir, S. and Khan, E. (2001) A geometric-primitives-based compression scheme for testingsystems-on-a-chip. VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001, 1.

Conference or Workshop Item

El-Maleh, A. and Arkasosy, B. and Landolsi, M.A. Interconnect-Efficient LDPC Code Design. In: Int’l Conf. on Microelectronics, Dec. 2006.

This list was generated on Wed Jul 30 08:01:32 2014 AST.