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    Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine

    (2006) Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine. Microelectronics, 2006. ICM '06. International conference, 1.

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    Abstract

    A feasibility study for implementing the AES encryption algorithm in hardware achieving 500 Gbits/s is presented. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution that is scalable.

    Item Type: Article
    Subjects: Petroleum
    Department: College of Computing and Mathematics > Computer Engineering
    Depositing User: Mr. Admin Admin
    Date Deposited: 24 Jun 2008 13:37
    Last Modified: 01 Nov 2019 14:06
    URI: http://eprints.kfupm.edu.sa/id/eprint/14483