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Data-flow expression evaluator for VLSI implementation.

Ghaffar, Faaez Mohammed. (1987) Data-flow expression evaluator for VLSI implementation. Masters thesis, King Fahd University of Petroleum and Minerals.


Arabic Abstract


English Abstract

This work involves the design and development of a numeric expression evaluating computing systems which can be added as a special purpose slave processor to a host computer. The Data-Flow Expression Evaluator (DFEE) would increase the performance of the host computer in terms of computation speed-up. The expression evaluation system is based on data-flow computing architecture. The architecture is further developed into a highly parallel circular pipelined computing architecture. This architecture is mapped into a Very Large Scale Integrated Circuit (VLSI) design which would be suitable for single chip VLSI implementation.

Item Type:Thesis (Masters)
Date:June 1987
Date Type:Completion
Divisions:College Of Engineering Sciences > Electrical Engineering Dept
Creators:Ghaffar, Faaez Mohammed.
Committee Advisor:Beckhoff, Gerhard F.
Committee Members:Zafar, Z. and Rahman, M. A. A.
ID Code:9911
Deposited By:KFUPM ePrints Admin
Deposited On:22 Jun 2008 16:52
Last Modified:25 Apr 2011 09:41

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