Ali, Syed Asaf Maruf (1994) Design and modeling of a real-time RISC processor in VHDL. Masters thesis, King Fahd University of Petroleum and Minerals.
Real-time systems re-characterized by high speed computation and strict timing constraints. Nowadays, powerful processors are capable of executing millions of instructions per second. These high speed processors can be utilized in the design of real-time systems which can benefit from their high performance in order to meet their strict timing constraints. This thesis is concerned with the study of real-time systems and their properties and determining the extent to which these real-time features are supported in currently available RISC processors. Once these features are identified a new instruction set is proposed which attempts to target these features at the instruction set level. The instruction set is optimized for real-time applications by executing instructions in a single cycle and supporting powerful bit manipulation. The instruction set and the data-path are modeled in VHDL (VHSIC Hardware Description Language) at the behavioral level.
|Item Type:||Thesis (Masters)|
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Ali, Syed Asaf Maruf|
|Committee Advisor:||Elleithy, Khaled M.|
|Committee Members:||Sait, Sadiq M. and Amin, Alaaeldin A. M. and Benten, M. S. T.|
|Deposited By:||KFUPM ePrints Admin|
|Deposited On:||22 Jun 2008 16:46|
|Last Modified:||25 Apr 2011 09:12|
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