AUTOMATIC WEINBERGER ARRAY SYNTHESIS FROM UAHPL DESCRIPTION

Abstract

Abstract A Weinberger array (WA) (Weinberger 1967) synthesis system is described that automatically generates WAs for combinational logic circuits modelled in Universal Hardware Programming Language (UAHPL) (Masud and Sait 1986). The system also minimizes the area required by the WA by performing row compaction. An algorithm similar to that used for channel routing is employed for compaction (Hashimoto and Stevens 1971). This convenient tool for designing combinational logic circuits models at a high level of abstraction and much of the procedure is automated. Descriptors: logic circuits