Sait, Sadiq M. and Al-Khulaiwi, FA AUTOMATIC WEINBERGER ARRAY SYNTHESIS FROM UAHPL DESCRIPTION. INTERNATIONAL JOURNAL OF ELECTRONICS 69 (2): 211-224 AUG 1990.
Abstract A Weinberger array (WA) (Weinberger 1967) synthesis system is described that automatically generates WAs for combinational logic circuits modelled in Universal Hardware Programming Language (UAHPL) (Masud and Sait 1986). The system also minimizes the area required by the WA by performing row compaction. An algorithm similar to that used for channel routing is employed for compaction (Hashimoto and Stevens 1971). This convenient tool for designing combinational logic circuits models at a high level of abstraction and much of the procedure is automated. Descriptors: logic circuits
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Sait, Sadiq M. and Al-Khulaiwi, FA|
|Deposited On:||11 Mar 2008 10:15|
|Last Modified:||12 Apr 2011 13:07|
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