Sait, Sadiq M. and Hasan, W. HARDWARE DESIGN AND VLSI IMPLEMENTATION OF A BYTE-WISE CRC GENERATOR CHIP. IEEE CIRCUITS AND DEVICES MAGAZINE 11 (2): 14-24 MAR 1995.
In this paper the ahrdware design and VLSi implementation of a byte-wise CRC generator is presented. The algorithm is based on the work presented in  in which a software implementation was proposed. The byte-wise CRC algorithm is translated to hardware and expressed in AHPL . The method used here calculates CRC on the fly and is muc faster than the look-up table method proposed by Lee. The chip is 8 times faster that the serial implementation of  with smaller hardware requirements (occupies lesser area). The number of clocl cycles required to generate and transmitany CRC (for an 8 hour bytemessage) is just two more that the time required to calculate it (in all 10 clocl pulses. The CRC chip can be used in anumber of applications. These include areas such as error detection and correction in data comunication, signature analysis and mass storage devices for parallel information transfers.
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Sait, Sadiq M. and Hasan, W.|
|Deposited On:||11 Mar 2008 08:45|
|Last Modified:||12 Apr 2011 13:07|
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