KFUPM ePrints

VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES

Sait, Sadiq M. and M. A. A., Khalid VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES. MICROPROCESSORS AND MICROSYSTEMS 19 (3): 139-146 APR 1995.

[img]
Preview
PDF
1629Kb

Abstract

A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue. Keywords: VLSI design; systolic tree architecture; automated layout



Item Type:Article
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Sait, Sadiq M. and M. A. A., Khalid
Email:sadiq@kfupm.edu.sa, UNSPECIFIED
ID Code:292
Deposited By:AbdulRahman
Deposited On:11 Mar 2008 07:53
Last Modified:12 Apr 2011 13:07

Repository Staff Only: item control page