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A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance

El-Maleh, Aiman H. and Kassab, Mark and Rajski, Janusz (1998) A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. 32nd Design Automation Congference. pp. 625-631.

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Abstract

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.



Item Type:Article
Date:June 1998
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:El-Maleh, Aiman H. and Kassab, Mark and Rajski, Janusz
Email:aimane@kfupm.edu.sa, mark_kassab@mentorg.com, janusz_rajski@mentor.com
ID Code:203
Deposited By:AIMAN HELMI EL-MALEH
Deposited On:04 Mar 2008 01:20
Last Modified:12 Apr 2011 13:06

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