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Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement

Sait, Sadiq M. and Youssef, H. and El-Maleh, Aiman H. Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. In: KFUPM Project Number COE/ITERATE/221, KFUPM.

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Item Type:Conference or Workshop Item (Other)
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Sait, Sadiq M. and Youssef, H. and El-Maleh, Aiman H.
Email:sadiq@kfupm.edu.sa, youssef@kfupm.edu.sa, aimane@kfupm.edu.sa
ID Code:201
Deposited By:AbdulRahman
Deposited On:08 Mar 2008 08:14
Last Modified:12 Apr 2011 13:07

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