Sait, Sadiq M. Area-Time Optimal Adder with Relative Placement Generator. In: Area-Time Optimal Adder with Relative Placement Generator.
This paper presents the design of a generator, for the production of area-time-optimal adders. A unique feature of this generator is that, it integrates synthesis and layout by providing relative placement information.. Relative placement information provides better support for structured layout and easier integration flow with data-path placer. Adders generated using the proposed generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. Adders of sizes 1 to 1024 bits are produced. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with Synopsys’ fast adders, a 20- 50% reduction in area with comparable delays are produced. This generator has been integrated into Synopsys high-performance datapath design tool Module Compiler.
|Item Type:||Conference or Workshop Item (Other)|
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Sait, Sadiq M.|
|Deposited On:||02 Mar 2008 09:00|
|Last Modified:||12 Apr 2011 13:07|
Repository Staff Only: item control page