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Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits

El-Maleh, Aiman H. and Osais, Yahya E. (2003) Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits. ACM Transactions on Design Automation of Electronic Systems, 8 (4). pp. 430-459.

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Abstract

Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this paper, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms.



Item Type:Article
Date:October 2003
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:El-Maleh, Aiman H. and Osais, Yahya E.
Email:aimane@kfupm.edu.sa, yosais@kfupm.edu.sa
ID Code:165
Deposited By:AIMAN HELMI EL-MALEH
Deposited On:01 Mar 2008 11:25
Last Modified:12 Apr 2011 13:06

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