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On Test Vector Reordering for Combinational Circuits

El-Maleh, Aiman H. and Osais, Yahya E. (2004) On Test Vector Reordering for Combinational Circuits. 16th International Conference on Microelectronics. 772 -775.

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Abstract

The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such away that reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexities of reordering procedures based on fault simulation without dropping. Experimental results demonstrate both the efficiency and effectiveness of our proposed technique.



Item Type:Article
Date:December 2004
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Information and Computer Science Dept
Creators:El-Maleh, Aiman H. and Osais, Yahya E.
Email:aimane@kfupm.edu.sa, yosais@kfupm.edu.sa
ID Code:164
Deposited By:AIMAN HELMI EL-MALEH
Deposited On:01 Mar 2008 02:49
Last Modified:12 Apr 2011 13:06

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