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A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip

El-Maleh, Aiman H. (2003) A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip. 10th IEEE International Conference on Electronics, Circuits and Systems,. pp. 599-602.

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Abstract

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequencydirected run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric- Primitives-Based compression technique.



Item Type:Article
Date:December 2003
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:El-Maleh, Aiman H.
Email:aimane@kfupm.edu.sa
ID Code:160
Deposited By:AIMAN HELMI EL-MALEH
Deposited On:29 Feb 2008 23:05
Last Modified:12 Apr 2011 13:06

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