KFUPM ePrints

Hardware design and VLSI implementation of a byte-wise CRCgenerator chip

Sait, Sadiq M. and Hasan, W. (1995) Hardware design and VLSI implementation of a byte-wise CRCgenerator chip. Consumer Electronics, IEEE Transactions on, 41.

[img]
Preview
PDF
18Kb
[img]Microsoft Word
26Kb

Abstract

The hardware design and VLSI implementation of a byte-wise CRC generator is presented. The algorithm is based on the work presented by Perez, Wismer and Becker (1983) in which a software implementation was proposed. The byte-wise CRC algorithm is translated to hardware and pressed in APHL (VLSI design automation language). The method used calculates CRC `on the fly' and is much faster then the look-up table method proposed by Lee (1981). The chip is 8 times faster than the serial implementation of Sait and Khan (see ibid., vol. 39, no.4, p.911-910, 1993) with smaller hardware requirements (occupies lesser area). The number of clock cycles required to generate and transmit any CRC (for an 8 byte message) is just two more than the time required to calculate it (in all 10 clock pulses). The CRC chip can be used in a number of applications. These include areas such as error detection and correction in data communications, signature analysis, and mass storage devices for parallel information transfers



Item Type:Article
Date:February 1995
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Sait, Sadiq M. and Hasan, W.
Email:sadiq@kfupm.edu.sa, UNSPECIFIED
ID Code:14649
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:44
Last Modified:12 Apr 2011 13:17

Repository Staff Only: item control page