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Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine

Bouhraoua, A. (2006) Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine. Microelectronics, 2006. ICM '06. International conference, 1.

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Abstract

A feasibility study for implementing the AES encryption algorithm in hardware achieving 500 Gbits/s is presented. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution that is scalable.



Item Type:Article
Date:December 2006
Date Type:Publication
Subjects:Petroleum
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Bouhraoua, A.
Email:abouh@ccse.kfupm.edu.sa
ID Code:14483
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:37
Last Modified:12 Apr 2011 13:14

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