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Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

Al-Yamani, A. and Devta-Prasanna, N. and Chmelar, E. and Grinchuk, M. and Gunda, A. (UNSPECIFIED) Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26.

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Abstract

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets



Item Type:Article
Date:UNSPECIFIED
Date Type:Publication
Subjects:Computer
Divisions:College Of Engineering Sciences > Electrical Engineering Dept
Creators:Al-Yamani, A. and Devta-Prasanna, N. and Chmelar, E. and Grinchuk, M. and Gunda, A.
ID Code:14310
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:31
Last Modified:12 Apr 2011 13:15

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