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Double-rail encoded self-timed adder with matched delays

Amin, A. and Maadi, F. (2003) Double-rail encoded self-timed adder with matched delays. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 3.

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Abstract

An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.



Item Type:Article
Date:December 2003
Date Type:Publication
Subjects:Computer
Divisions:College Of Engineering Sciences > Chemical Engineering Dept
Creators:Amin, A. and Maadi, F.
ID Code:14143
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:24
Last Modified:12 Apr 2011 13:14

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