El-Maleh, Aiman H. and Al-Suwaiyan, Ali (2002) An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 20’th IEEE VLSI Test Symposium. pp. 53-59.
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.
|Divisions:||College Of Computer Sciences and Engineering > Information and Computer Science Dept|
|Creators:||El-Maleh, Aiman H. and Al-Suwaiyan, Ali|
|Deposited By:||AIMAN HELMI EL-MALEH|
|Deposited On:||27 Feb 2008 00:53|
|Last Modified:||12 Apr 2011 13:06|
Repository Staff Only: item control page