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A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder

Sait, Sadiq M. and Damati, A.F. and Rahman, M. (1989) A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder. Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean, 1.

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Abstract

A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modeled in AHPL to verify functional correctness. Implementation details are discussed. It is found that the proposed systolic design compares favorably with previous implementations of Viterbi decoders in terms of speed and modularity



Item Type:Article
Date:April 1989
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Sait, Sadiq M. and Damati, A.F. and Rahman, M.
Email:sadiq@kfupm.edu.sa, UNSPECIFIED, UNSPECIFIED
ID Code:14067
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:21
Last Modified:12 Apr 2011 13:15

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