KFUPM ePrints

A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links

Elrabaa, Muhammad (2006) A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links. Microelectronics, 2006. ICM '06. International conference, 1.

[img]Microsoft Word


A new all-digital circuit scheme for clock and data re-timing functions for on-chip high-speed source synchronous data communications, such as in burst-mode data transmission over a network-on-chip is introduced. The new technique is non-PLL-based and is capable of retiming the output clock with the received data within one data transition. Being fully digital makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spice?? simulations using a 0.13??m digital CMOS technology.

Item Type:Article
Date:December 2006
Date Type:Publication
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Elrabaa, Muhammad
ID Code:14026
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:19
Last Modified:12 Apr 2011 13:14

Repository Staff Only: item control page