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A STATIC TEST COMPACTION TECHNIQUE FOR COMBINATIONAL CIRCUITS BASED ON INDEPENDENT FAULT CLUSTERING

Osais, Yahya E. and El-Maleh, Aiman H. (2003) A STATIC TEST COMPACTION TECHNIQUE FOR COMBINATIONAL CIRCUITS BASED ON INDEPENDENT FAULT CLUSTERING. 10th IEEE International Conference on Electronics, Circuits and Systems. pp. 1316-1319.

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Abstract

Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm.



Item Type:Article
Date:December 2003
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Information and Computer Science Dept
Creators:Osais, Yahya E. and El-Maleh, Aiman H.
Email:yosais@kfupm.edu.sa, aimane@kfupm.edu.sa
ID Code:140
Deposited By:AIMAN HELMI EL-MALEH
Deposited On:27 Feb 2008 00:40
Last Modified:12 Apr 2011 13:06

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