An Efficient Test Relaxation Technique for Synchronous Sequential Circuits

Abstract

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.