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A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures

El-Maleh, Aiman H. and Osais, Yahya E. (2001) A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures. Int. Symp. on Circuits and Systems. pp. 550-553.

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Abstract

Recently, a new Built-In Self Test (BIST) methodology based on balanced bistable sequential kernels has been proposed that reduces the area overhead and performance degradation associated with the conventional BILBO-oriented BIST methodology. This new methodology guarantees high fault coverage but requires special test sequences and test pattern generator (TPG) designs. In this paper, we demonstrate the use of the retiming technique in designing TPGs for balanced bistable sequential kernels. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the designed TPGs in achieving higher fault coverage than the conventional maximal-length LFSR TPGs.



Item Type:Article
Date:2001
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Information and Computer Science Dept
Creators:El-Maleh, Aiman H. and Osais, Yahya E.
Email:aimane@kfupm.edu.sa, yosais@kfupm.edu.sa
ID Code:138
Deposited By:AIMAN HELMI EL-MALEH
Deposited On:27 Feb 2008 00:12
Last Modified:12 Apr 2011 13:06

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