Sait, Sadiq M. and Farooqui, Aamir A. and Beckhoff, G. F. (1995) A Novel Technique for Fast Multiplication. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.
In this paper we present the design of a new high speed multiplication unit. THe design is based on non-overlapped scanning of 3-bit fields of the multiplier. In this algorithm the partial product of the multiplicand and three bits of the multiplier are pre-calculated using only only hardwired shitfs. These partial products are then added using a treee of carry-save-adders, and finaly the sum and carry vectors are added using a carry-look-ahead adder, In case of 2's complement multiplication the tree of carry-save-adders also recieves a correction output produced in parallel with the partial products. The algorithms is modelled in a hardware description language and its VLSI chip implemetned. The performance of the new design is compared with other recent ones proposed in literature.
|Item Type:||Conference or Workshop Item (Other)|
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Sait, Sadiq M. and Farooqui, Aamir A. and Beckhoff, G. F.|
|Email:||firstname.lastname@example.org, email@example.com, UNSPECIFIED|
|Deposited On:||26 Feb 2008 15:40|
|Last Modified:||12 Apr 2011 13:07|
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