A Novel Technique for Fast Multiplication

Abstract

In this paper we present the design of a new high speed multiplication unit. THe design is based on non-overlapped scanning of 3-bit fields of the multiplier. In this algorithm the partial product of the multiplicand and three bits of the multiplier are pre-calculated using only only hardwired shitfs. These partial products are then added using a treee of carry-save-adders, and finaly the sum and carry vectors are added using a carry-look-ahead adder, In case of 2's complement multiplication the tree of carry-save-adders also recieves a correction output produced in parallel with the partial products. The algorithms is modelled in a hardware description language and its VLSI chip implemetned. The performance of the new design is compared with other recent ones proposed in literature.