Timing Driven Genetic Algorithm for Placement

Abstract

In this paper we present a timing -driven placer for standard-cell IC design. The placement algorithm follows the genetic pradigm. At early generations, the search is biased towards solutions with superior timing characteristics. As the algorithm starts converging towards generations with acceptable delay properties, the objective is dynamically adjusted towards optimizing area and routability. Experiments with test circuits demonstrate delay performance improvement by upto 20%. Without any noticeable loss in solution quality, sizebale reduction in runtime is obtained when population size is allowed to decrease in a controlled manner whenever the search hits a plateau.