High Speed Low Power GF(2k) Elliptic Curve Cryptography Processor Architecture

Abstract

A new elliptic curve cryptographic processor architecture is proposed in this paper. It gives a choice of performance base depending on the importance of speed and/or power consumption. This flexibility is accomplished by utilizing the normal parallelism in the elliptic curve point operations. Scalable multipliers are adopted to compensate for the extra hardware due to parallelism instead of using the conventional parallel multipliers. It is shown in the paper that this parallelism can be exploited either to increase the speed of operation or to reduce power consumption by reducing the frequency of operation.