KFUPM ePrints

Performance Driven Standard-cell Placement Using the Genetic Algorithm

Youssef, H. and Sait, Sadiq M. and Nassar, K. and Benten, M. S. (1995) Performance Driven Standard-cell Placement Using the Genetic Algorithm. In: Fifth Great Lakes Symposium on VLSI, GLSVLSI'95, Buffalo, USA.

[img]
Preview
PDF
575Kb

Abstract

Current placement systems attempt to optimize several objectives, namely area, connection lenght, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propogation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of criticality. Experiments with test circuits demonstrate delay performance improvement by upto 20%



Item Type:Conference or Workshop Item (Other)
Date:March 1995
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Youssef, H. and Sait, Sadiq M. and Nassar, K. and Benten, M. S.
Email:youssef@kfupm.edu.sa, sadiq@kfupm.edu.sa, UNSPECIFIED, UNSPECIFIED
ID Code:130
Deposited By:AbdulRahman
Deposited On:26 Feb 2008 15:09
Last Modified:12 Apr 2011 13:07

Repository Staff Only: item control page