In this section

    Performance Driven Standard-cell Placement Using the Genetic Algorithm

    (1995) Performance Driven Standard-cell Placement Using the Genetic Algorithm. In: Fifth Great Lakes Symposium on VLSI, GLSVLSI'95, Buffalo, USA.

    [img]
    Preview
    		 PDF
    Youssef_GLS_March1995.pdf
    Download (589kB) | Preview

    Abstract

    Current placement systems attempt to optimize several objectives, namely area, connection lenght, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propogation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of criticality. Experiments with test circuits demonstrate delay performance improvement by upto 20%

    Item Type: Conference or Workshop Item (Other)
    Subjects: Computer
    Department: College of Computing and Mathematics > Computer Engineering
    Depositing User: AbdulRahman
    Date Deposited: 26 Feb 2008 12:09
    Last Modified: 01 Nov 2019 13:22
    URI: http://eprints.kfupm.edu.sa/id/eprint/130