Sait, Sadiq M. and Elleithy, K. and Hasan, M. (1994) Design of a Cell Library for Formal High-level Synthesis. In: IEEE Melecon'94.
In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the Realization Specification Language (RSL)  as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplayer is presented to illustrate the application of the cell library.
|Item Type:||Conference or Workshop Item (Other)|
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Sait, Sadiq M. and Elleithy, K. and Hasan, M.|
|Email:||firstname.lastname@example.org, UNSPECIFIED, UNSPECIFIED|
|Deposited On:||26 Feb 2008 14:48|
|Last Modified:||12 Apr 2011 13:07|
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