A State Machine Synthesizer with Weinberger Arrays

Abstract

In this paper we desribe the development of a digital circuit synthesis program. The program accpets the transition table of a state machine and returns equations for an implementation that assumes a sum-of-product next-state and output functions. From the equations for the next-state and output functions, an nMOS VLSI layout for Weinberger araay (WA) is generated. D flip-flops are assumed for memory calculations can be avoided and layout are generated automatically from state table descriptions.