KFUPM ePrints

New Fault Models and Efficient BIST Algorithm for Dual Port Memories

Amin, Alaaeldin and Abdel-Aal, R.E. and Osman, M. Y. and Al-Muhtaseb, Husni (1997) New Fault Models and Efficient BIST Algorithm for Dual Port Memories. IEEE Transations on CAD of Integrated Circuits and Systems, 16 (9). pp. 987-1000.

Full text not available from this repository.

Abstract

The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(√n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF)



Item Type:Article
Date:September 1997
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Information and Computer Science Dept
Creators:Amin, Alaaeldin and Abdel-Aal, R.E. and Osman, M. Y. and Al-Muhtaseb, Husni
Email:amindin@kfupm.edu.sa, radwan@kfupm.edu.sa, UNSPECIFIED, UNSPECIFIED
ID Code:1237
Deposited By:Obaid-Ur-Rehman Khattak
Deposited On:28 Apr 2008 15:23
Last Modified:12 Apr 2011 13:08

Repository Staff Only: item control page