Design and Analysis of a High Speed Sense Amplifier for Single Transistor Non-Volatile Memory Cells

Abstract

Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds equal to or better than those achievable by memory arrays using two transistors per cell. Other circuit techniques were used to improve the circuit-noise immunity as well as sensitivity to critical mask misalignments including the use of output latches, dummy bit lines and decoded odd/even reference-memory-cell selection. The circuit was implemented on a 32k EPROM memory chip using 1.5 μm N-well CMOS process