A Systolic Algorithm for VLSI Design of a Rate Viterbi Decoder

Abstract

Viterbi decoding algorithm is one of the most widely use forward error correcting techniques in digital communication. hardware realization of the Viterbi algorithm are complex, and implementation is difficult, expensive and or slow. Systolic architectures are simple modular and regular and are well suited for VLSI implementation. In this paper a new systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. THe first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modelled in AHPL to verify functional correctness. Implementation details are discussed. The proposed architecture is compared with previous implementations of the Viterbi algorithm.