PERFORMANCE AND LOW POWER DRIVEN VLSI STANDARD CELL PLACEMENT USING TABU SEARCH

Abstract

We engineer a well known optimization technique namely Tabu Search (TS) [1] for the performance and low power driven VLSI standard cell placement problem [2], [3]. The above problem is of multiobjective nature since threee possibly conflicting objectives are considered to be optimized subject to the constraint of layout width. These objectives are power disipation, timing performance, and interconnect wire length a hard problem to solve. Due to imprecise nature of objectives values, fuzzy logic is incorporated in the design of aggregating function. The above technique is applied to the benchmark circuits and teh results are compared with Adaptive-bias Simulated Evolution (SimE) approach.