Nassar, Khaled Muhammad Walid (1994) Timing driven placement algorithm for standard-cell design. Masters thesis, King Fahd University of Petroleum and Minerals.
![[img]](http://eprints.kfupm.edu.sa/style/images/fileicons/application_pdf.png)
| PDF 3301Kb |
Arabic Abstract
-
English Abstract
The performance of present VLSI circuits is dominated by interconnect delays. Therefore, there is a great demand to design new placement tools to incorporate performance measures of the circuits. This thesis presents a new method of solving the problem of timing driven placement for standard-cell design style using Genetic Algorithm approach. This problem is solved in an iterative manner using genetic operators. The timing problem is modeled in a path oriented manner, where timing constraints are imposed on total path delays which include both cell and interconnect delays. Improvements upto 17.7% were obtained with respect to clock speed-up of the tested examples compared to the results obtained by area driven placement tools. However, the improvements in timing have resulted in a little increase between 1.4% and 9.1% in the area of the chip after routing. The thesis work is embodied in a program called Timing Driven Genetic Algorithm for Placement (TDGAP)
| Item Type: | Thesis (Masters) |
|---|---|
| Date: | June 1994 |
| Date Type: | Completion |
| Subjects: | Computer |
| Divisions: | College Of Computer Sciences and Engineering > Computer Engineering Dept |
| Creators: | Nassar, Khaled Muhammad Walid |
| Committee Advisor: | Sait, Sadiq M. |
| Committee Members: | Youssef, Habib and Benten, M. S. T. |
| ID Code: | 10233 |
| Deposited By: | KFUPM ePrints Admin |
| Deposited On: | 22 Jun 2008 16:59 |
| Last Modified: | 26 Apr 2011 07:59 |
Repository Staff Only: item control page